--- onnv-129.orig/usr/src/lib/libsmbios/common/mapfile-vers Tue Dec 1 09:41:45 2009 +++ onnv-129/usr/src/lib/libsmbios/common/mapfile-vers Sat Mar 19 00:52:22 2011 @@ -137,3 +137,12 @@ local: *; }; + +SUNWprivate_1.2 { + global: + smbios_info_obdevse; + smbios_obdev_name; + smbios_obdev_desc; + smbios_processor_flag_name; + smbios_processor_flag_desc; +} SUNWprivate_1.1; --- onnv-129.orig/usr/src/uts/common/sys/smbios.h Tue Dec 1 09:42:07 2009 +++ onnv-129/usr/src/uts/common/sys/smbios.h Sat Mar 19 00:51:51 2011 @@ -37,6 +37,11 @@ * In short, do not user this header file or these routines for any purpose. */ +/* + * Last Update: 2011-02-01 Version 2.7.1 http://dmtf.org/standards/smbios + * @see smbios_impl.h + * @see smb_info.c + */ #ifndef _SYS_SMBIOS_H #define _SYS_SMBIOS_H @@ -47,7 +52,7 @@ #endif /* - * SMBIOS Structure Table Entry Point. See DSP0134 2.1.1 for more information. + * SMBIOS Structure Table Entry Point. See DSP0134 5.2.1 for more information. * The structure table entry point is located by searching for the anchor. */ #pragma pack(1) @@ -79,8 +84,8 @@ /* * Structure type codes. The comments next to each type include an (R) note to - * indicate a structure that is required as of SMBIOS v2.3 and an (O) note to - * indicate a structure that is obsolete as of SMBIOS v2.3. + * indicate a structure that is required as of SMBIOS v2.7.1 and an (O) note to + * indicate a structure that is obsolete as of SMBIOS v2.7.1. */ #define SMB_TYPE_BIOS 0 /* BIOS information (R) */ #define SMB_TYPE_SYSTEM 1 /* system information (R) */ @@ -92,7 +97,7 @@ #define SMB_TYPE_CACHE 7 /* processor cache (R) */ #define SMB_TYPE_PORT 8 /* port connector */ #define SMB_TYPE_SLOT 9 /* upgradeable system slot (R) */ -#define SMB_TYPE_OBDEVS 10 /* on-board devices */ +#define SMB_TYPE_OBDEVS 10 /* on-board devices (O) */ #define SMB_TYPE_OEMSTR 11 /* OEM string table */ #define SMB_TYPE_SYSCONFSTR 12 /* system configuration string table */ #define SMB_TYPE_LANG 13 /* BIOS language information */ @@ -102,7 +107,7 @@ #define SMB_TYPE_MEMDEVICE 17 /* memory device (R) */ #define SMB_TYPE_MEMERR32 18 /* 32-bit memory error information */ #define SMB_TYPE_MEMARRAYMAP 19 /* memory array mapped address (R) */ -#define SMB_TYPE_MEMDEVICEMAP 20 /* memory device mapped address (R) */ +#define SMB_TYPE_MEMDEVICEMAP 20 /* memory device mapped address */ #define SMB_TYPE_POINTDEV 21 /* built-in pointing device */ #define SMB_TYPE_BATTERY 22 /* portable battery */ #define SMB_TYPE_RESET 23 /* system reset settings */ @@ -122,6 +127,9 @@ #define SMB_TYPE_MEMCHAN 37 /* memory channel */ #define SMB_TYPE_IPMIDEV 38 /* IPMI device information */ #define SMB_TYPE_POWERSUP 39 /* system power supply */ +#define SMB_TYPE_ADDINFO 40 /* additional information */ +#define SMB_TYPE_OBDEVSE 41 /* onboard devices extended information */ +#define SMB_TYPE_MGMTCHI 42 /* management controller host interface */ #define SMB_TYPE_INACTIVE 126 /* inactive table entry */ #define SMB_TYPE_EOT 127 /* end of table */ @@ -169,7 +177,7 @@ #define SMB_CONT_MAX 255 /* maximum contained objects */ /* - * SMBIOS Bios Information. See DSP0134 Section 3.3.1 for more information. + * SMBIOS Bios Information (Type 0). See DSP0134 Section 7.1. * smbb_romsize is converted from the implementation format into bytes. */ typedef struct smbios_bios { @@ -219,8 +227,8 @@ #define SMB_BIOSFL_I10_CGA 0x40000000 /* int 0x10 CGA svcs */ #define SMB_BIOSFL_NEC_PC98 0x80000000 /* NEC PC-98 */ -#define SMB_BIOSXB_1 0 /* bios extension byte 1 (3.3.1.2.1) */ -#define SMB_BIOSXB_2 1 /* bios extension byte 2 (3.3.1.2.2) */ +#define SMB_BIOSXB_1 0 /* bios extension byte 1 (7.1.2.1) */ +#define SMB_BIOSXB_2 1 /* bios extension byte 2 (7.1.2.2) */ #define SMB_BIOSXB_BIOS_MAJ 2 /* bios major version */ #define SMB_BIOSXB_BIOS_MIN 3 /* bios minor version */ #define SMB_BIOSXB_ECFW_MAJ 4 /* extended ctlr f/w major version */ @@ -238,9 +246,11 @@ #define SMB_BIOSXB2_BBOOT 0x01 /* BIOS Boot Specification supported */ #define SMB_BIOSXB2_FKNETSVC 0x02 /* F-key Network Svc boot supported */ #define SMB_BIOSXB2_ETCDIST 0x04 /* Enable Targeted Content Distrib. */ +#define SMB_BIOSXB2_UEFI 0x08 /* UEFI Specification supported */ +#define SMB_BIOSXB2_VM 0x10 /* SMBIOS table describes a virtual machine */ /* - * SMBIOS Bios Information. See DSP0134 Section 3.3.2 for more information. + * SMBIOS System Information (Type 1). See DSP0134 Section 7.2. * The current set of smbs_wakeup values is defined after the structure. */ typedef struct smbios_system { @@ -262,8 +272,8 @@ #define SMB_WAKEUP_AC 0x08 /* AC power restored */ /* - * SMBIOS Base Board description. See DSP0134 Section 3.3.3 for more - * information. smbb_flags and smbb_type definitions are below. + * SMBIOS Baseboard (or Module) Information (Type 2). See DSP0134 Section 7.3. + * smbb_flags and smbb_type definitions are below. */ typedef struct smbios_bboard { id_t smbb_chassis; /* chassis containing this board */ @@ -293,7 +303,7 @@ #define SMB_BBT_INTER 0xD /* interconnect board */ /* - * SMBIOS Chassis description. See DSP0134 Section 3.3.4 for more information. + * SMBIOS System Enclosures or Chassis (Type 3). See DSP0134 Section 7.4. * We move the lock bit of the type field into smbc_lock for easier processing. */ typedef struct smbios_chassis { @@ -304,10 +314,11 @@ uint8_t smbc_psstate; /* power supply state */ uint8_t smbc_thstate; /* thermal state */ uint8_t smbc_security; /* security status */ - uint8_t smbc_uheight; /* enclosure height in U's */ + uint8_t smbc_uheight; /* enclosure height in rack units */ uint8_t smbc_cords; /* number of power cords */ uint8_t smbc_elems; /* number of element records (n) */ uint8_t smbc_elemlen; /* length of contained element (m) */ + const char *smbc_sku; /* SKU number */ } smbios_chassis_t; #define SMB_CHT_OTHER 0x01 /* other */ @@ -354,7 +365,7 @@ #define SMB_CHSC_EIENAB 0x05 /* external interface enabled */ /* - * SMBIOS Processor description. See DSP0134 Section 3.3.5 for more details. + * SMBIOS Processor Information (Type 4). See DSP0134 Section 7.5. * If the L1, L2, or L3 cache handle is -1, the cache information is unknown. * If the handle refers to something of size 0, that type of cache is absent. * @@ -376,6 +387,10 @@ id_t smbp_l1cache; /* L1 cache handle */ id_t smbp_l2cache; /* L2 cache handle */ id_t smbp_l3cache; /* L3 cache handle */ + uint8_t smbp_corecount; /* # of cores per processor socket */ + uint8_t smbp_coresenabled; /* # of enabled cores per processor socket */ + uint8_t smbp_threadcount; /* number of threads per processor socket */ + uint16_t smbp_cflags; /* processor characteristics (SMB_PRC_*) */ } smbios_processor_t; #define SMB_PRT_OTHER 0x01 /* other */ @@ -388,9 +403,9 @@ #define SMB_PRV_LEGACY(v) (!((v) & 0x80)) /* legacy voltage mode */ #define SMB_PRV_FIXED(v) ((v) & 0x80) /* fixed voltage mode */ -#define SMB_PRV_5V 0x01 /* 5V is supported */ -#define SMB_PRV_33V 0x02 /* 3.3V is supported */ -#define SMB_PRV_29V 0x04 /* 2.9V is supported */ +#define SMB_PRV_5V 0x01 /* 5 V is supported */ +#define SMB_PRV_33V 0x02 /* 3.3 V is supported */ +#define SMB_PRV_29V 0x04 /* 2.9 V is supported */ #define SMB_PRV_VOLTAGE(v) ((v) & 0x7f) @@ -404,6 +419,15 @@ #define SMB_PRS_IDLE 0x4 /* waiting to be enabled */ #define SMB_PRS_OTHER 0x7 /* other */ +#define SMB_PRC_RESERVED 0x00 /* reserved */ +#define SMB_PRC_UNKNOWN 0x01 /* unknown */ +#define SMB_PRC_64BIT 0x02 /* 64-bit capable */ +#define SMB_PRC_MC 0x04 /* multi-core */ +#define SMB_PRC_HT 0x08 /* hardware thread */ +#define SMB_PRC_NX 0x10 /* execution protection */ +#define SMB_PRC_VT 0x20 /* enhanced virtualization */ +#define SMB_PRC_PM 0x40 /* power/performance control */ + #define SMB_PRU_OTHER 0x01 /* other */ #define SMB_PRU_UNKNOWN 0x02 /* unknown */ #define SMB_PRU_DAUGHTER 0x03 /* daughter board */ @@ -428,6 +452,24 @@ #define SMB_PRU_S1 0x16 /* socket S1 */ #define SMB_PRU_AM2 0x17 /* socket AM2 */ #define SMB_PRU_F 0x18 /* socket F */ +#define SMB_PRU_LGA1366 0x19 /* socket LGA1366 */ +#define SMB_PRU_G34 0x1A /* socket G34 */ +#define SMB_PRU_AM3 0x1B /* socket AM3 */ +#define SMB_PRU_C32 0x1C /* socket C32 */ +#define SMB_PRU_LGA1156 0x1D /* socket LGA1156 */ +#define SMB_PRU_LGA1567 0x1E /* socket LGA1567 */ +#define SMB_PRU_PGA988A 0x1F /* socket PGA988A */ +#define SMB_PRU_BGA1288 0x20 /* socket BGA1288 */ +#define SMB_PRU_rPGA988B 0x21 /* socket rPGA988B */ +#define SMB_PRU_BGA1023 0x22 /* socket BGA1023 */ +#define SMB_PRU_BGA1224 0x23 /* socket BGA1224 */ +#define SMB_PRU_BGA1155 0x24 /* socket BGA1155 */ +#define SMB_PRU_LGA1356 0x25 /* socket LGA1356 */ +#define SMB_PRU_LGA2011 0x26 /* socket LGA2011 */ +#define SMB_PRU_FS1 0x27 /* socket FS1 */ +#define SMB_PRU_FS2 0x28 /* socket FS2 */ +#define SMB_PRU_FM1 0x29 /* socket FM1 */ +#define SMB_PRU_FM2 0x2A /* socket FM2 */ #define SMB_PRF_OTHER 0x01 /* other */ #define SMB_PRF_UNKNOWN 0x02 /* unknown */ @@ -448,6 +490,9 @@ #define SMB_PRF_PENTIUMIII 0x11 /* Pentium III */ #define SMB_PRF_M1 0x12 /* M1 */ #define SMB_PRF_M2 0x13 /* M2 */ +#define SMB_PRF_CELERON_M 0x14 /* Celeron M */ +#define SMB_PRF_PENTIUM4_HT 0x15 /* Pentium 4 HT */ + #define SMB_PRF_DURON 0x18 /* AMD Duron */ #define SMB_PRF_K5 0x19 /* K5 */ #define SMB_PRF_K6 0x1A /* K6 */ @@ -464,6 +509,11 @@ #define SMB_PRF_PPC_620 0x25 /* PowerPC 620 */ #define SMB_PRF_PPC_704 0x26 /* PowerPC x704 */ #define SMB_PRF_PPC_750 0x27 /* PowerPC 750 */ +#define SMB_PRF_CORE_DUO 0x28 /* Core Duo */ +#define SMB_PRF_CORE_DUO_M 0x29 /* Core Duo Mobile */ +#define SMB_PRF_CORE_SOLO_M 0x2A /* Core Solo Mobile */ +#define SMB_PRF_ATOM 0x2B /* Atom */ + #define SMB_PRF_ALPHA 0x30 /* Alpha */ #define SMB_PRF_ALPHA_21064 0x31 /* Alpha 21064 */ #define SMB_PRF_ALPHA_21066 0x32 /* Alpha 21066 */ @@ -472,6 +522,14 @@ #define SMB_PRF_ALPHA_21164A 0x35 /* Alpha 21164a */ #define SMB_PRF_ALPHA_21264 0x36 /* Alpha 21264 */ #define SMB_PRF_ALPHA_21364 0x37 /* Alpha 21364 */ +#define SMB_PRF_TURION2_UDCM 0x38 /* Turion II Ultra Dual-Core Mobile */ +#define SMB_PRF_TURION2_DCM 0x39 /* Turion II Dual-Core Mobile */ +#define SMB_PRF_TURION2_DCMF 0x3A /* Turion II Dual-Core M */ +#define SMB_PRF_OPTERON_6100 0x3B /* Opteron 6100 Series */ +#define SMB_PRF_OPTERON_4100 0x3C /* Opteron 4100 Series */ +#define SMB_PRF_OPTERON_6200 0x3D /* Opteron 6200 Series */ +#define SMB_PRF_OPTERON_4200 0x3E /* Opteron 4200 Series */ + #define SMB_PRF_MIPS 0x40 /* MIPS */ #define SMB_PRF_MIPS_R4000 0x41 /* MIPS R4000 */ #define SMB_PRF_MIPS_R4200 0x42 /* MIPS R4200 */ @@ -478,6 +536,11 @@ #define SMB_PRF_MIPS_R4400 0x43 /* MIPS R4400 */ #define SMB_PRF_MIPS_R4600 0x44 /* MIPS R4600 */ #define SMB_PRF_MIPS_R10000 0x45 /* MIPS R10000 */ +#define SMB_PRF_AMD_C 0x46 /* AMD C-Series */ +#define SMB_PRF_AMD_E 0x47 /* AMD E-Series */ +#define SMB_PRF_AMD_S 0x48 /* AMD S-Series */ +#define SMB_PRF_AMD_G 0x49 /* AMD G-Series */ + #define SMB_PRF_SPARC 0x50 /* SPARC */ #define SMB_PRF_SUPERSPARC 0x51 /* SuperSPARC */ #define SMB_PRF_MICROSPARCII 0x52 /* microSPARC II */ @@ -487,6 +550,7 @@ #define SMB_PRF_USIIi 0x56 /* UltraSPARC IIi */ #define SMB_PRF_USIII 0x57 /* UltraSPARC III */ #define SMB_PRF_USIIIi 0x58 /* UltraSPARC IIIi */ + #define SMB_PRF_68040 0x60 /* 68040 */ #define SMB_PRF_68XXX 0x61 /* 68XXX */ #define SMB_PRF_68000 0x62 /* 68000 */ @@ -493,14 +557,29 @@ #define SMB_PRF_68010 0x63 /* 68010 */ #define SMB_PRF_68020 0x64 /* 68020 */ #define SMB_PRF_68030 0x65 /* 68030 */ + #define SMB_PRF_HOBBIT 0x70 /* Hobbit */ + #define SMB_PRF_TM5000 0x78 /* Crusoe TM5000 */ #define SMB_PRF_TM3000 0x79 /* Crusoe TM3000 */ #define SMB_PRF_TM8000 0x7A /* Efficeon TM8000 */ + #define SMB_PRF_WEITEK 0x80 /* Weitek */ + #define SMB_PRF_ITANIC 0x82 /* Itanium */ -#define SMB_PRF_ATHLON64 0x83 /* Athlon64 */ +#define SMB_PRF_ATHLON64 0x83 /* Athlon 64 */ #define SMB_PRF_OPTERON 0x84 /* Opteron */ +#define SMB_PRF_SEMPRON 0x85 /* Sempron */ +#define SMB_PRF_TURION64_M 0x86 /* Turion 64 Mobile */ +#define SMB_PRF_OPTERON_DC 0x87 /* Dual-Core Opteron */ +#define SMB_PRF_ATHLON64_X2DC 0x88 /* Athlon 64 X2 Dual-Core */ +#define SMB_PRF_TURION64_X2M 0x89 /* Turion 64 X2 Mobile */ +#define SMB_PRF_OPTERON_QC 0x8A /* Quad-Core Opteron */ +#define SMB_PRF_OPTERON_3G 0x8B /* 3rd Generation Opteron */ +#define SMB_PRF_PHENOM_FXQC 0x8C /* Phenom FX Quad-Core */ +#define SMB_PRF_PHENOM_X4QC 0x8D /* Phenom X4 Quad-Core */ +#define SMB_PRF_PHENOM_X2DC 0x8E /* Phenom X2 Dual-Core */ +#define SMB_PRF_ATHLON_X2DC 0x8F /* Athlon X2 Dual-Core */ #define SMB_PRF_PA 0x90 /* PA-RISC */ #define SMB_PRF_PA8500 0x91 /* PA-RISC 8500 */ #define SMB_PRF_PA8000 0x92 /* PA-RISC 8000 */ @@ -508,46 +587,106 @@ #define SMB_PRF_PA7200 0x94 /* PA-RISC 7200 */ #define SMB_PRF_PA7100LC 0x95 /* PA-RISC 7100LC */ #define SMB_PRF_PA7100 0x96 /* PA-RISC 7100 */ + #define SMB_PRF_V30 0xA0 /* V30 */ +#define SMB_PRF_XEON_3200QC 0xA1 /* Quad-Core Xeon 3200 Series */ +#define SMB_PRF_XEON_3000DC 0xA2 /* Dual-Core Xeon 3000 Series */ +#define SMB_PRF_XEON_5300QC 0xA3 /* Quad-Core Xeon 5300 Series */ +#define SMB_PRF_XEON_5100DC 0xA4 /* Dual-Core Xeon 5100 Series */ +#define SMB_PRF_XEON_5000DC 0xA5 /* Dual-Core Xeon 5000 Series */ +#define SMB_PRF_XEON_DCLV 0xA6 /* Dual-Core Xeon LV */ +#define SMB_PRF_XEON_DCULV 0xA7 /* Dual-Core Xeon ULV */ +#define SMB_PRF_XEON_7100DC 0xA8 /* Dual-Core Xeon 7100 Series */ +#define SMB_PRF_XEON_5400QC 0xA9 /* Quad-Core Xeon 5400 Series */ +#define SMB_PRF_XEON_QC 0xAA /* Quad-Core Xeon */ +#define SMB_PRF_XEON_5200DC 0xAB /* Dual-Core Xeon 5200 Series */ +#define SMB_PRF_XEON_7200DC 0xAC /* Dual-Core Xeon 7200 Series */ +#define SMB_PRF_XEON_7300QC 0xAD /* Quad-Core Xeon 7300 Series */ +#define SMB_PRF_XEON_7400QC 0xAE /* Quad-Core Xeon 7400 Series */ +#define SMB_PRF_XEON_7400MC 0xAF /* Multi-Core Xeon 7400 Series */ #define SMB_PRF_PENTIUMIII_XEON 0xB0 /* Pentium III Xeon */ #define SMB_PRF_PENTIUMIII_SS 0xB1 /* Pentium III with SpeedStep */ #define SMB_PRF_P4 0xB2 /* Pentium 4 */ -#define SMB_PRF_XEON 0xB3 /* Intel Xeon */ +#define SMB_PRF_XEON 0xB3 /* Xeon */ #define SMB_PRF_AS400 0xB4 /* AS400 */ -#define SMB_PRF_XEON_MP 0xB5 /* Intel Xeon MP */ -#define SMB_PRF_ATHLON_XP 0xB6 /* AMD Athlon XP */ -#define SMB_PRF_ATHLON_MP 0xB7 /* AMD Athlon MP */ +#define SMB_PRF_XEON_MP 0xB5 /* Xeon MP */ +#define SMB_PRF_ATHLON_XP 0xB6 /* Athlon XP */ +#define SMB_PRF_ATHLON_MP 0xB7 /* Athlon MP */ #define SMB_PRF_ITANIC2 0xB8 /* Itanium 2 */ #define SMB_PRF_PENTIUM_M 0xB9 /* Pentium M */ #define SMB_PRF_CELERON_D 0xBA /* Celeron D */ #define SMB_PRF_PENTIUM_D 0xBB /* Pentium D */ #define SMB_PRF_PENTIUM_EE 0xBC /* Pentium Extreme Edition */ -#define SMB_PRF_CORE 0xBD /* Intel Core */ -#define SMB_PRF_CORE2 0xBF /* Intel Core 2 */ +#define SMB_PRF_CORE_SOLO 0xBD /* Core Solo */ +#define SMB_PRF_CORE2_DUO 0xBF /* Core 2 Duo */ + +#define SMB_PRF_CORE2_SOLO 0xC0 /* Core 2 Solo */ +#define SMB_PRF_CORE2_E 0xC1 /* Core 2 Extreme */ +#define SMB_PRF_CORE2_Q 0xC2 /* Core 2 Quad */ +#define SMB_PRF_CORE2_EM 0xC3 /* Core 2 Extreme Mobile */ +#define SMB_PRF_CORE2_DUO_M 0xC4 /* Core 2 Duo Mobile */ +#define SMB_PRF_CORE2_SOLO_M 0xC5 /* Core 2 Solo Mobile */ +#define SMB_PRF_COREi7 0xC6 /* Core i7 */ +#define SMB_PRF_CELERON_DC 0xC7 /* Dual-Core Celeron */ #define SMB_PRF_IBM390 0xC8 /* IBM 390 */ #define SMB_PRF_G4 0xC9 /* G4 */ #define SMB_PRF_G5 0xCA /* G5 */ -#define SMB_PRF_ESA390 0xCB /* ESA390 */ +#define SMB_PRF_ESA390 0xCB /* ESA/390 G6 */ #define SMB_PRF_ZARCH 0xCC /* z/Architecture */ +#define SMB_PRF_COREi5 0xCD /* Core i5 */ +#define SMB_PRF_COREi3 0xCE /* Core i3 */ + #define SMB_PRF_C7M 0xD2 /* VIA C7-M */ #define SMB_PRF_C7D 0xD3 /* VIA C7-D */ #define SMB_PRF_C7 0xD4 /* VIA C7 */ #define SMB_PRF_EDEN 0xD5 /* VIA Eden */ +#define SMB_PRF_XEON_MC 0xD6 /* Multi-Core Xeon */ +#define SMB_PRF_XEON_3XXXDC 0xD7 /* Dual-Core Xeon 3xxx Series */ +#define SMB_PRF_XEON_3XXXQC 0xD8 /* Quad-Core Xeon 3xxx Series */ +#define SMB_PRF_NANO 0xD9 /* VIA Nano */ +#define SMB_PRF_XEON_5XXXDC 0xDA /* Dual-Core Xeon 5xxx Series */ +#define SMB_PRF_XEON_5XXXQC 0xDB /* Quad-Core Xeon 5xxx Series */ + +#define SMB_PRF_XEON_7XXXDC 0xDD /* Dual-Core Xeon 7xxx Series */ +#define SMB_PRF_XEON_7XXXQC 0xDE /* Quad-Core Xeon 7xxx Series */ +#define SMB_PRF_XEON_7XXXMC 0xDF /* Multi-Core Xeon 7xxx Series */ +#define SMB_PRF_XEON_3400MC 0xE0 /* Multi-Core Xeon 3400 Series */ + +#define SMB_PRF_OPTERON_QCE 0xE6 /* Embedded Opteron Quad-Core */ +#define SMB_PRF_PHENOM_X3 0xE7 /* Phenom Triple-Core */ +#define SMB_PRF_TURION_UDCM 0xE8 /* Turion Ultra Dual-Core Mobile */ +#define SMB_PRF_TURION_DCM 0xE9 /* Turion Dual-Core Mobile */ +#define SMB_PRF_ATHLON_DC 0xEA /* Athlon Dual-Core */ +#define SMB_PRF_SEMPRON_SI 0xEB /* Sempron SI */ +#define SMB_PRF_PHENOM2 0xEC /* Phenom II */ +#define SMB_PRF_ATHLON2 0xED /* Athlon II */ +#define SMB_PRF_OPTERON_HC 0xEE /* Six-Core Opteron */ +#define SMB_PRF_SEMPRON_M 0xEF /* Sempron M */ + #define SMB_PRF_I860 0xFA /* i860 */ #define SMB_PRF_I960 0xFB /* i960 */ + #define SMB_PRF_SH3 0x104 /* SH-3 */ #define SMB_PRF_SH4 0x105 /* SH-4 */ + #define SMB_PRF_ARM 0x118 /* ARM */ #define SMB_PRF_SARM 0x119 /* StrongARM */ + #define SMB_PRF_6X86 0x12C /* 6x86 */ #define SMB_PRF_MEDIAGX 0x12D /* MediaGX */ + #define SMB_PRF_MII 0x12E /* MII */ + #define SMB_PRF_WINCHIP 0x140 /* WinChip */ + #define SMB_PRF_DSP 0x15E /* DSP */ + #define SMB_PRF_VIDEO 0x1F4 /* Video Processor */ +/* Type 5 and 6 skipped since obsolete */ + /* - * SMBIOS Cache Information. See DSP0134 Section 3.3.8 for more information. + * SMBIOS Cache Information (Type 7). See DSP0134 Section 7.8. * If smba_size is zero, this indicates the specified cache is not present. */ typedef struct smbios_cache { @@ -594,6 +733,12 @@ #define SMB_CAA_FULL 0x06 /* fully associative */ #define SMB_CAA_8WAY 0x07 /* 8-way set associative */ #define SMB_CAA_16WAY 0x08 /* 16-way set associative */ +#define SMB_CAA_12WAY 0x09 /* 12-way set associative */ +#define SMB_CAA_24WAY 0x0A /* 24-way set associative */ +#define SMB_CAA_32WAY 0x0B /* 32-way set associative */ +#define SMB_CAA_48WAY 0x0C /* 48-way set associative */ +#define SMB_CAA_64WAY 0x0D /* 64-way set associative */ +#define SMB_CAA_20WAY 0x0E /* 20-way set associative */ #define SMB_CAM_WT 0x00 /* write-through */ #define SMB_CAM_WB 0x01 /* write-back */ @@ -609,7 +754,7 @@ #define SMB_CAF_SOCKETED 0x02 /* cache is socketed */ /* - * SMBIOS Port Information. See DSP0134 Section 3.3.9 for more information. + * SMBIOS Port Connector Information (Type 8). See DSP0134 Section 7.9. * The internal reference designator string is also mapped to the location. */ typedef struct smbios_port { @@ -701,8 +846,8 @@ #define SMB_POT_OTHER 0xFF /* other */ /* - * SMBIOS Slot Information. See DSP0134 Section 3.3.10 for more information. - * See DSP0134 3.3.10.5 for how to interpret the value of smbl_id. + * SMBIOS System Slots (Type 9). See DSP0134 Section 7.10. + * See DSP0134 7.10.5 for how to interpret the value of smbl_id. */ typedef struct smbios_slot { const char *smbl_name; /* reference designation */ @@ -713,6 +858,10 @@ uint16_t smbl_id; /* slot ID */ uint8_t smbl_ch1; /* slot characteristics 1 */ uint8_t smbl_ch2; /* slot characteristics 2 */ + uint16_t smbl_group; /* segment group */ + uint8_t smbl_bus; /* bus */ + uint8_t smbl_device; /* device */ + uint8_t smbl_function; /* function */ } smbios_slot_t; #define SMB_SLT_OTHER 0x01 /* other */ @@ -740,11 +889,23 @@ #define SMB_SLT_PC98_LB 0xA3 /* PC-98/Local Bus */ #define SMB_SLT_PC98_C 0xA4 /* PC-98/Card */ #define SMB_SLT_PCIE 0xA5 /* PCI Express */ -#define SMB_SLT_PCIE1 0xA6 /* PCI Express x1 */ -#define SMB_SLT_PCIE2 0xA7 /* PCI Express x2 */ -#define SMB_SLT_PCIE4 0xA8 /* PCI Express x4 */ -#define SMB_SLT_PCIE8 0xA9 /* PCI Express x8 */ -#define SMB_SLT_PCIE16 0xAA /* PCI Express x16 */ +#define SMB_SLT_PCIE_X1 0xA6 /* PCI Express x1 */ +#define SMB_SLT_PCIE_X2 0xA7 /* PCI Express x2 */ +#define SMB_SLT_PCIE_X4 0xA8 /* PCI Express x4 */ +#define SMB_SLT_PCIE_X8 0xA9 /* PCI Express x8 */ +#define SMB_SLT_PCIE_X16 0xAA /* PCI Express x16 */ +#define SMB_SLT_PCIE2 0xAB /* PCI Express 2 */ +#define SMB_SLT_PCIE2_X1 0xAC /* PCI Express 2 x1 */ +#define SMB_SLT_PCIE2_X2 0xAD /* PCI Express 2 x2 */ +#define SMB_SLT_PCIE2_X4 0xAE /* PCI Express 2 x4 */ +#define SMB_SLT_PCIE2_X8 0xAF /* PCI Express 2 x8 */ +#define SMB_SLT_PCIE2_X16 0xB0 /* PCI Express 2 x16 */ +#define SMB_SLT_PCIE3 0xB1 /* PCI Express 3 */ +#define SMB_SLT_PCIE3_X1 0xB2 /* PCI Express 3 x1 */ +#define SMB_SLT_PCIE3_X2 0xB3 /* PCI Express 3 x2 */ +#define SMB_SLT_PCIE3_X4 0xB4 /* PCI Express 3 x4 */ +#define SMB_SLT_PCIE3_X8 0xB5 /* PCI Express 3 x8 */ +#define SMB_SLT_PCIE3_X16 0xB6 /* PCI Express 3 x16 */ #define SMB_SLW_OTHER 0x01 /* other */ #define SMB_SLW_UNKNOWN 0x02 /* unknown */ @@ -772,8 +933,8 @@ #define SMB_SLL_LONG 0x04 /* long length */ #define SMB_SLCH1_UNKNOWN 0x01 /* characteristics unknown */ -#define SMB_SLCH1_5V 0x02 /* provides 5.0V */ -#define SMB_SLCH1_33V 0x04 /* provides 3.3V */ +#define SMB_SLCH1_5V 0x02 /* provides 5.0 V */ +#define SMB_SLCH1_33V 0x04 /* provides 3.3 V */ #define SMB_SLCH1_SHARED 0x08 /* opening shared with other slot */ #define SMB_SLCH1_PC16 0x10 /* slot supports PC Card-16 */ #define SMB_SLCH1_PCCB 0x20 /* slot supports CardBus */ @@ -785,10 +946,12 @@ #define SMB_SLCH2_SMBUS 0x04 /* slot supports SMBus signal */ /* - * SMBIOS On-Board Device Information. See DSP0134 Section 3.3.11 for more - * information. Any number of on-board device sections may be present, each - * containing one or more records. The smbios_info_obdevs() function permits - * the caller to retrieve one or more of the records from a given section. + * SMBIOS On-Board Device Information (Type 10). See DSP0134 Section 7.11. + * Obsolete since revision 2.6 - Type 41 should be used instead. However vendors + * may choose to implement both. + * Any number of on-board device sections may be present, each containing one + * or more records. The smbios_info_obdevs() function permits the caller to + * retrieve one or more of the records from a given section. */ typedef struct smbios_obdev { const char *smbd_name; /* description string for this device */ @@ -808,10 +971,25 @@ #define SMB_OBT_SAS 0x0A /* sas */ /* - * SMBIOS BIOS Language Information. See DSP0134 Section 3.3.14 for more - * information. The smbios_info_strtab() function can be applied using a - * count of smbla_num to retrieve the other possible language settings. + * SMBIOS On-Board Device Information (Type 41). See DSP0134 Section 7.42. */ +typedef struct smbios_obdeve { + const char *smbd_name; /* description string for this device */ + uint8_t smbd_type; /* type code (SMB_OBT_*) */ + uint8_t smbd_enabled; /* boolean (device is enabled) */ + uint8_t smbd_instance; /* device type instance */ + uint16_t smbd_group; /* segment group */ + uint8_t smbd_bus; /* bus */ + uint8_t smbd_device; /* device */ + uint8_t smbd_function; /* function */ +} smbios_obdeve_t; + + +/* + * SMBIOS BIOS Language Information (Type 13). See DSP0134 Section 7.14. + * The smbios_info_strtab() function can be applied using a count of smbla_num + * to retrieve the other possible language settings. + */ typedef struct smbios_lang { const char *smbla_cur; /* current language setting */ uint_t smbla_fmt; /* language name format (see below) */ @@ -822,8 +1000,8 @@ #define SMB_LFMT_SHORT 1 /* */ /* - * SMBIOS System Event Log Information. See DSP0134 Section 3.3.16 for more - * information. Accessing the event log itself requires additional interfaces. + * SMBIOS System Event Log (Type 15). See DSP0134 Section 7.16. + * Accessing the event log itself requires additional interfaces. */ typedef struct smbios_evtype { uint8_t smbevt_ltype; /* log type */ @@ -864,8 +1042,8 @@ #define SMB_EVHF_F1 1 /* DMTF log header type 1 */ /* - * SMBIOS Physical Memory Array Information. See DSP0134 Section 3.3.17 for - * more information. This describes a collection of physical memory devices. + * SMBIOS Physical Memory Array (Type 16). See DSP0134 Section 7.17. + * This describes a collection of physical memory devices. */ typedef struct smbios_memarray { uint8_t smbma_location; /* physical device location */ @@ -910,8 +1088,8 @@ #define SMB_MAE_CRC 0x07 /* CRC */ /* - * SMBIOS Memory Device Information. See DSP0134 Section 3.3.18 for more - * information. One or more of these structures are associated with each + * SMBIOS Memory Device (Type 17). See DSP0134 Section 7.18. + * One or more of these structures are associated with each * smbios_memarray_t. A structure is present even for unpopulated sockets. * Unknown values are set to -1. A smbmd_size of 0 indicates unpopulated. * WARNING: Some BIOSes appear to export the *maximum* size of the device @@ -928,9 +1106,11 @@ uint8_t smbmd_type; /* memory type */ uint8_t smbmd_pad; /* padding */ uint32_t smbmd_flags; /* flags (see below) */ - uint32_t smbmd_speed; /* speed in nanoseconds */ + uint32_t smbmd_speed; /* speed in MHz */ const char *smbmd_dloc; /* physical device locator string */ const char *smbmd_bloc; /* physical bank locator string */ + uint8_t smbmd_rank; /* rank */ + uint16_t smbmd_cfgspeed; /* configured speed in MHz */ } smbios_memdevice_t; #define SMB_MDFF_OTHER 0x01 /* other */ @@ -969,6 +1149,8 @@ #define SMB_MDT_DDR 0x12 /* DDR */ #define SMB_MDT_DDR2 0x13 /* DDR2 */ #define SMB_MDT_DDR2FBDIMM 0x14 /* DDR2 FBDIMM */ +#define SMB_MDT_DDR3 0x18 /* DDR3 */ +#define SMB_MDT_FBD2 0x19 /* FBD2 */ #define SMB_MDF_OTHER 0x0002 /* other */ #define SMB_MDF_UNKNOWN 0x0004 /* unknown */ @@ -982,10 +1164,12 @@ #define SMB_MDF_WDRAM 0x0400 /* Window DRAM */ #define SMB_MDF_CDRAM 0x0800 /* Cache DRAM */ #define SMB_MDF_NV 0x1000 /* non-volatile */ +#define SMB_MDF_REG 0x2000 /* registered (buffered) */ +#define SMB_MDF_UNBUF 0x4000 /* unbuffered (unregistered) */ /* - * SMBIOS Memory Array Mapped Address. See DSP0134 Section 3.3.20 for more - * information. We convert start/end addresses into addr/size for convenience. + * SMBIOS Memory Array Mapped Address (Type 19). See DSP0134 Section 7.20. + * We convert start/end addresses into addr/size for convenience. */ typedef struct smbios_memarrmap { id_t smbmam_array; /* physical memory array handle */ @@ -995,8 +1179,8 @@ } smbios_memarrmap_t; /* - * SMBIOS Memory Device Mapped Address. See DSP0134 Section 3.3.21 for more - * information. We convert start/end addresses into addr/size for convenience. + * SMBIOS Memory Device Mapped Address (Type 20). See DSP0134 Section 7.21. + * We convert start/end addresses into addr/size for convenience. */ typedef struct smbios_memdevmap { id_t smbmdm_device; /* memory device handle */ @@ -1009,8 +1193,8 @@ } smbios_memdevmap_t; /* - * SMBIOS Hardware Security Settings. See DSP0134 Section 3.3.25 for more - * information. Only one such record will be present in the SMBIOS. + * SMBIOS Hardware Security Settings (Type 24). See DSP0134 Section 7.25. + * Only one such record will be present in the SMBIOS. */ typedef struct smbios_hwsec { uint8_t smbh_pwr_ps; /* power-on password status */ @@ -1025,9 +1209,9 @@ #define SMB_HWSEC_PS_UNKNOWN 0x03 /* password status unknown */ /* - * SMBIOS System Boot Information. See DSP0134 Section 3.3.33 for more - * information. The contents of the data varies by type and is undocumented - * from the perspective of DSP0134 -- it seems to be left as vendor-specific. + * SMBIOS System Boot Information (Type 32). See DSP0134 Section 7.33. + * The contents of the data varies by type and is undocumented from the + * perspective of DSP0134 -- it seems to be left as vendor-specific. * The (D) annotation next to SMB_BOOT_* below indicates possible data payload. */ typedef struct smbios_boot { @@ -1053,7 +1237,7 @@ #define SMB_BOOT_PROD_HI 255 /* high end of product-specific range */ /* - * SMBIOS IPMI Device Information. See DSP0134 Section 3.3.39 and also + * SMBIOS IPMI Device Information (Type 38). See DSP0134 Section 7.39 and also * Appendix C1 of the IPMI specification for more information on this record. */ typedef struct smbios_ipmi { @@ -1128,7 +1312,10 @@ #define SMB_VERSION_23 0x0203 /* SMBIOS encoding for DMTF spec 2.3 */ #define SMB_VERSION_24 0x0204 /* SMBIOS encoding for DMTF spec 2.4 */ -#define SMB_VERSION SMB_VERSION_24 /* SMBIOS latest version definitions */ +#define SMB_VERSION_25 0x0205 /* SMBIOS encoding for DMTF spec 2.5 */ +#define SMB_VERSION_26 0x0206 /* SMBIOS encoding for DMTF spec 2.6 */ +#define SMB_VERSION_27 0x0207 /* SMBIOS encoding for DMTF spec 2.7 */ +#define SMB_VERSION SMB_VERSION_27 /* SMBIOS latest version definitions */ #define SMB_O_NOCKSUM 0x1 /* do not verify header checksums */ #define SMB_O_NOVERS 0x2 /* do not verify header versions */ @@ -1185,6 +1372,7 @@ extern int smbios_info_port(smbios_hdl_t *, id_t, smbios_port_t *); extern int smbios_info_slot(smbios_hdl_t *, id_t, smbios_slot_t *); extern int smbios_info_obdevs(smbios_hdl_t *, id_t, int, smbios_obdev_t *); +extern int smbios_info_obdevse(smbios_hdl_t *, id_t, smbios_obdeve_t *); extern int smbios_info_strtab(smbios_hdl_t *, id_t, int, const char *[]); extern id_t smbios_info_lang(smbios_hdl_t *, smbios_lang_t *); extern id_t smbios_info_eventlog(smbios_hdl_t *, smbios_evlog_t *); @@ -1261,7 +1449,12 @@ extern const char *smbios_port_conn_desc(uint_t); extern const char *smbios_port_type_desc(uint_t); +extern const char *smbios_obdev_name(uint_t); +extern const char *smbios_obdev_desc(uint_t); + extern const char *smbios_processor_family_desc(uint_t); +extern const char *smbios_processor_flag_name(uint_t); +extern const char *smbios_processor_flag_desc(uint_t); extern const char *smbios_processor_status_desc(uint_t); extern const char *smbios_processor_type_desc(uint_t); extern const char *smbios_processor_upgrade_desc(uint_t); --- onnv-129.orig/usr/src/uts/common/sys/smbios_impl.h Tue Dec 1 09:42:07 2009 +++ onnv-129/usr/src/uts/common/sys/smbios_impl.h Sat Mar 19 03:31:30 2011 @@ -136,8 +136,17 @@ uint8_t smbpr_serial; /* serial number */ uint8_t smbpr_asset; /* asset tag */ uint8_t smbpr_part; /* part number */ + uint8_t smbpr_corecount; /* # of cores per processor socket */ + uint8_t smbpr_coresenabled; /* # of enabled cores per processor socket */ + uint8_t smbpr_threadcount; /* number of threads per processor socket */ + uint16_t smbpr_cflags; /* Processor Characteristics */ + uint16_t smbpr_family2; /* Processor Family 2 */ } smb_processor_t; +#define SMB_PRF_FAMILY2 0xFE /* use family 2 */ +#define SMB_PROCESSOR_FAMILY(s) (((s).smbpr_family == SMB_PRF_FAMILY2) \ + ? (s).smbpr_family2 : (s).smbpr_family) + typedef struct smb_cache { smb_header_t smbca_hdr; /* structure header */ uint8_t smbca_socket; /* socket designation */ @@ -153,7 +162,7 @@ } smb_cache_t; /* - * Convert encoded cache size to bytes: DSP0134 Section 3.3.8 explains the + * Convert encoded cache size to bytes: DSP0134 Section 7.8 explains the * encoding. The highest bit is 0 for 1k units, 1 for 64k units, and this * macro decodes the value into bytes for exporting to our clients. */ @@ -185,13 +194,28 @@ uint16_t smbsl_id; /* slot ID */ uint8_t smbsl_ch1; /* slot characteristics 1 */ uint8_t smbsl_ch2; /* slot characteristics 2 */ + uint16_t smbsl_group; /* Segment Group Number */ + uint8_t smbsl_bus; /* Bus Number */ + uint8_t smbsl_devfn; /* Device/Function Number */ } smb_slot_t; +#define SMB_SLOT_DEVICE(v) (((v) == 0xff) ? 0xff : (v) >> 3) /* Bits 7:3 */ +#define SMB_SLOT_FUNC(v) (((v) == 0xff) ? 0xff : (v) & 0x7) /* Bits 2:0 */ + typedef struct smb_obdev { uint8_t smbob_type; /* encoded type and enable bit */ - uint8_t smbob_name; /* descriptiong string */ + uint8_t smbob_name; /* description string */ } smb_obdev_t; +typedef struct smb_obdeve { + uint8_t smbob_name; /* description string */ + uint8_t smbob_type; /* encoded type and enable bit */ + uint8_t smbob_instance; /* device type instance */ + uint16_t smbob_group; /* Segment Group Number */ + uint8_t smbob_bus; /* Bus Number */ + uint8_t smbob_devfn; /* Device/Function Number */ +} smb_obdeve_t; + #define SMB_OBT_ENABLED 0x80 /* enable bit within smbob_type */ typedef struct smb_strtab { @@ -230,8 +254,13 @@ uint32_t smbmarr_cap; /* maximum capacity */ uint16_t smbmarr_err; /* error handle */ uint16_t smbmarr_ndevs; /* number of slots or sockets */ + uint64_t smbmarr_ecap; /* extended maximum capacity */ } smb_memarray_t; +#define SMB_MA_MAXVAL 0x80000000 +#define SMB_MA_CAPACITY(s) ((s).smbmarr_cap == SMB_MA_MAXVAL \ + ? (s).smbmarr_ecap : (((uint64_t)(s).smbmarr_cap) << 10)) + typedef struct smb_memarrmap { smb_header_t smbamap_hdr; /* structure header */ uint32_t smbamap_start; /* starting address in kilobytes */ @@ -238,8 +267,16 @@ uint32_t smbamap_end; /* ending address in kilobytes */ uint16_t smbamap_array; /* physical memory array handle */ uint8_t smbamap_width; /* partition width */ + uint64_t smbamap_estart; /* extended starting address in bytes */ + uint64_t smbamap_eend; /* extended ending address in bytes */ } smb_memarrmap_t; +#define SMB_MAM_MAXADDR 0xffffffff +#define SMB_MAM_STARTADDR(s) ((s).smbamap_start == SMB_MAM_MAXADDR \ + ? (s).smbamap_estart : (((uint64_t)(s).smbamap_start) << 10)) +#define SMB_MAM_ENDADDR(s) ((s).smbamap_end == SMB_MAM_MAXADDR \ + ? (s).smbamap_eend : (((uint64_t)(s).smbamap_end) << 10)) + typedef struct smb_memdevice { smb_header_t smbmdev_hdr; /* structure header */ uint16_t smbmdev_array; /* array handle */ @@ -258,10 +295,15 @@ uint8_t smbmdev_serial; /* serial number */ uint8_t smbmdev_asset; /* asset tag */ uint8_t smbmdev_part; /* part number */ + uint8_t smbmdev_attr; /* attributes */ + uint32_t smbmdev_esize; /* extended size - complements smbmdev_size */ + uint16_t smbmdev_cfgspeed; /* Configured Memory Clock Speed */ } smb_memdevice_t; -#define SMB_MDS_KBYTES 0x8000 /* size in specified in kilobytes */ +#define SMB_MEMDEVICE_RANK(v) ((v) & 0xf) +#define SMB_MDS_KBYTES 0x8000 /* size specified in kilobytes */ + typedef struct smb_memdevmap { smb_header_t smbdmap_hdr; /* structure header */ uint32_t smbdmap_start; /* starting address in kilobytes */ @@ -271,8 +313,16 @@ uint8_t smbdmap_rpos; /* row position */ uint8_t smbdmap_ipos; /* interleave position */ uint8_t smbdmap_idepth; /* interleave depth */ + uint64_t smbdmap_estart; /* extended starting address in bytes */ + uint64_t smbdmap_eend; /* extended ending address in bytes */ } smb_memdevmap_t; +#define SMB_MDM_MAXADDR 0xffffffff +#define SMB_MDM_STARTADDR(s) ((s).smbdmap_start == SMB_MDM_MAXADDR \ + ? (s).smbdmap_estart : (((uint64_t)(s).smbdmap_start) << 10)) +#define SMB_MDM_ENDADDR(s) ((s).smbdmap_end == SMB_MDM_MAXADDR \ + ? (s).smbdmap_eend : (((uint64_t)(s).smbdmap_end) << 10)) + typedef struct smb_battery { smb_header_t smbbat_hdr; /* structure header */ uint8_t smbbat_loc; /* location */ --- onnv-129.orig/usr/src/common/smbios/smb_open.c Tue Dec 1 09:41:38 2009 +++ onnv-129/usr/src/common/smbios/smb_open.c Fri Mar 18 04:30:29 2011 @@ -82,6 +82,9 @@ switch (version) { case SMB_VERSION_23: case SMB_VERSION_24: + case SMB_VERSION_25: + case SMB_VERSION_26: + case SMB_VERSION_27: break; default: return (smb_open_error(shp, errp, ESMB_VERSION)); --- onnv-129.orig/usr/src/common/smbios/smb_info.c Tue Dec 1 09:41:38 2009 +++ onnv-129/usr/src/common/smbios/smb_info.c Sat Mar 19 02:59:07 2011 @@ -107,7 +107,7 @@ offsetof(smb_chassis_t, smbch_serial), offsetof(smb_chassis_t, smbch_asset), 0, - 0, + 0, /* offset to SKU# is variable: &smbn_cv + smbbb_cn * smbbb_cm */ offsetof(smb_chassis_t, smbch_cn), SMB_CONT_BYTE, offsetof(smb_chassis_t, smbch_cv) }, @@ -433,7 +433,10 @@ chp->smbc_cords = ch.smbch_cords; chp->smbc_elems = ch.smbch_cn; chp->smbc_elemlen = ch.smbch_cm; - + if (ch.smbch_cn > 0 && ch.smbch_cm > 0) { + chp->smbc_sku = + smb_strptr(stp, ch.smbch_cv[ch.smbch_cn * ch.smbch_cm]); + } return (0); } @@ -454,8 +457,9 @@ pp->smbp_cpuid = p.smbpr_cpuid; pp->smbp_type = p.smbpr_type; - pp->smbp_family = p.smbpr_family; + pp->smbp_family = SMB_PROCESSOR_FAMILY(p); pp->smbp_voltage = p.smbpr_voltage; + pp->smbp_clkspeed = p.smbpr_clkspeed; pp->smbp_maxspeed = p.smbpr_maxspeed; pp->smbp_curspeed = p.smbpr_curspeed; pp->smbp_status = p.smbpr_status; @@ -463,7 +467,10 @@ pp->smbp_l1cache = p.smbpr_l1cache; pp->smbp_l2cache = p.smbpr_l2cache; pp->smbp_l3cache = p.smbpr_l3cache; - + pp->smbp_corecount = p.smbpr_corecount; + pp->smbp_coresenabled = p.smbpr_coresenabled; + pp->smbp_threadcount = p.smbpr_threadcount; + pp->smbp_cflags = p.smbpr_cflags; return (0); } @@ -551,7 +558,13 @@ sp->smbl_id = s.smbsl_id; sp->smbl_ch1 = s.smbsl_ch1; sp->smbl_ch2 = s.smbsl_ch2; - + if (stp->smbst_hdr->smbh_len < sizeof(s)) { + s.smbsl_group = s.smbsl_bus = s.smbsl_devfn = 0xff; + } + sp->smbl_group = s.smbsl_group; + sp->smbl_bus = s.smbsl_bus; + sp->smbl_device = SMB_SLOT_DEVICE(s.smbsl_devfn); + sp->smbl_function = SMB_SLOT_FUNC(s.smbsl_devfn); return (0); } @@ -581,6 +594,33 @@ return (m); } +int +smbios_info_obdevse(smbios_hdl_t *shp, id_t id, smbios_obdeve_t *obp) +{ + const smb_struct_t *stp = smb_lookup_id(shp, id); + smb_obdeve_t op; + + if (stp == NULL) + return (-1); /* errno is set for us */ + + if (stp->smbst_hdr->smbh_type != SMB_TYPE_OBDEVSE) + return (smb_set_errno(shp, ESMB_TYPE)); + + smb_info_bcopy(stp->smbst_hdr, &op, sizeof (op)); + bzero(obp, sizeof (smb_obdeve_t)); + + obp->smbd_name = smb_strptr(stp, op.smbob_name); + obp->smbd_type = op.smbob_type & ~SMB_OBT_ENABLED; + obp->smbd_enabled = (op.smbob_type & SMB_OBT_ENABLED) != 0; + obp->smbd_instance = op.smbob_instance; + obp->smbd_group = op.smbob_group; + obp->smbd_bus = op.smbob_bus; + obp->smbd_device = SMB_SLOT_DEVICE(op.smbob_devfn); + obp->smbd_function = SMB_SLOT_FUNC(op.smbob_devfn); + + return (0); +} + /* * The implementation structures for OEMSTR, SYSCONFSTR, and LANG all use the * first byte to indicate the size of a string table at the end of the record. @@ -687,12 +727,8 @@ map->smbma_ecc = m.smbmarr_ecc; map->smbma_ndevs = m.smbmarr_ndevs; map->smbma_err = m.smbmarr_err; + map->smbma_size = SMB_MA_CAPACITY(m); - if (m.smbmarr_cap != 0x80000000) - map->smbma_size = (uint64_t)m.smbmarr_cap * 1024; - else - map->smbma_size = 0; /* unknown */ - return (0); } @@ -713,9 +749,8 @@ map->smbmam_array = m.smbamap_array; map->smbmam_width = m.smbamap_width; - map->smbmam_addr = (uint64_t)m.smbamap_start * 1024; - map->smbmam_size = (uint64_t) - (m.smbamap_end - m.smbamap_start + 1) * 1024; + map->smbmam_addr = SMB_MAM_STARTADDR(m); + map->smbmam_size = SMB_MAM_ENDADDR(m) - map->smbmam_addr + 1024; return (0); } @@ -746,8 +781,12 @@ mdp->smbmd_size *= 1024; else mdp->smbmd_size *= 1024 * 1024; - } else + } else if (m.smbmdev_esize == 0) { mdp->smbmd_size = -1ULL; /* size unknown */ + } else { + mdp->smbmd_size = (uint64_t)(m.smbmdev_esize & 0x7fffffff); + mdp->smbmd_size <<= 30; + } mdp->smbmd_form = m.smbmdev_form; mdp->smbmd_set = m.smbmdev_set; @@ -756,8 +795,11 @@ mdp->smbmd_dloc = smb_strptr(stp, m.smbmdev_dloc); mdp->smbmd_bloc = smb_strptr(stp, m.smbmdev_bloc); + mdp->smbmd_rank = SMB_MEMDEVICE_RANK(m.smbmdev_attr); if (m.smbmdev_speed != 0) - mdp->smbmd_speed = 1000 / m.smbmdev_speed; /* MHz -> nsec */ + mdp->smbmd_speed = m.smbmdev_speed; + if (m.smbmdev_cfgspeed != 0) + mdp->smbmd_cfgspeed = m.smbmdev_cfgspeed; return (0); } @@ -779,9 +821,8 @@ mdp->smbmdm_device = m.smbdmap_device; mdp->smbmdm_arrmap = m.smbdmap_array; - mdp->smbmdm_addr = (uint64_t)m.smbdmap_start * 1024; - mdp->smbmdm_size = (uint64_t) - (m.smbdmap_end - m.smbdmap_start + 1) * 1024; + mdp->smbmdm_addr = SMB_MDM_STARTADDR(m); + mdp->smbmdm_size = SMB_MDM_ENDADDR(m) - mdp->smbmdm_addr + 1024; mdp->smbmdm_rpos = m.smbdmap_rpos; mdp->smbmdm_ipos = m.smbdmap_ipos; mdp->smbmdm_idepth = m.smbdmap_idepth; --- onnv-129.orig/usr/src/common/smbios/mktables.sh Tue Dec 1 09:41:38 2009 +++ onnv-129/usr/src/common/smbios/mktables.sh Fri Mar 18 22:18:51 2011 @@ -48,9 +48,11 @@ SMB_EVFL_ smbios_evlog_flag_name uint_t SMB_IPMI_F_ smbios_ipmi_flag_name uint_t SMB_MDF_ smbios_memdevice_flag_name uint_t -SMB_TYPE_ smbios_type_name uint_t +SMB_OBT_ smbios_obdev_name uint_t +SMB_PRC_ smbios_processor_flag_name uint_t SMB_SLCH1_ smbios_slot_ch1_name uint_t SMB_SLCH2_ smbios_slot_ch2_name uint_t +SMB_TYPE_ smbios_type_name uint_t ' desc_funcs=' @@ -81,8 +83,10 @@ SMB_MDF_ smbios_memdevice_flag_desc uint_t SMB_MDFF_ smbios_memdevice_form_desc uint_t SMB_MDT_ smbios_memdevice_type_desc uint_t +SMB_OBT_ smbios_obdev_desc uint_t SMB_POC_ smbios_port_conn_desc uint_t SMB_POT_ smbios_port_type_desc uint_t +SMB_PRC_ smbios_processor_flag_desc uint_t SMB_PRF_ smbios_processor_family_desc uint_t SMB_PRS_ smbios_processor_status_desc uint_t SMB_PRT_ smbios_processor_type_desc uint_t --- onnv-129.orig/usr/src/cmd/smbios/smbios.c Tue Dec 1 09:41:35 2009 +++ onnv-129/usr/src/cmd/smbios/smbios.c Sat Mar 19 01:46:08 2011 @@ -135,7 +135,7 @@ oprintf(fp, "%sNot Supported\n", s); break; default: - oprintf(fp, "%s%u\n", s, (uint_t)id); + oprintf(fp, "%ssee ID %u\n", s, (uint_t)id); } } @@ -303,6 +303,7 @@ (void) smbios_info_chassis(shp, id, &c); + oprintf(fp, " SKU Number: %s\n", c.smbc_sku ? c.smbc_sku : ""); oprintf(fp, " OEM Data: 0x%x\n", c.smbc_oemdata); oprintf(fp, " Lock Present: %s\n", c.smbc_lock ? "Y" : "N"); @@ -318,7 +319,7 @@ desc_printf(smbios_chassis_state_desc(c.smbc_thstate), fp, " Thermal State: 0x%x", c.smbc_thstate); - oprintf(fp, " Chassis Height: %uu\n", c.smbc_uheight); + oprintf(fp, " Chassis Height: %u RU\n", c.smbc_uheight); oprintf(fp, " Power Cords: %u\n", c.smbc_cords); elem_cnt = c.smbc_elems; @@ -377,6 +378,16 @@ SMB_PRSTATUS_PRESENT(p.smbp_status) ? "Populated" : "Not Populated"); + if (p.smbp_corecount != 0) { + oprintf(fp, " Cores: %u\n", p.smbp_corecount); + oprintf(fp, " Cores Enabled: %u\n", p.smbp_coresenabled); + oprintf(fp, " Hardware Threads: %u\n", p.smbp_threadcount); + } + if (p.smbp_cflags != 0) { + flag_printf(fp, "Characteristics", p.smbp_cflags, + sizeof (p.smbp_cflags) * NBBY, + smbios_processor_flag_name, smbios_processor_flag_desc); + } desc_printf(smbios_processor_status_desc(status), fp, " Processor Status: %u", status); @@ -384,33 +395,33 @@ oprintf(fp, " Supported Voltages:"); switch (p.smbp_voltage) { case SMB_PRV_5V: - oprintf(fp, " 5.0V"); + oprintf(fp, " 5.0 V"); break; case SMB_PRV_33V: - oprintf(fp, " 3.3V"); + oprintf(fp, " 3.3 V"); break; case SMB_PRV_29V: - oprintf(fp, " 2.9V"); + oprintf(fp, " 2.9 V"); break; } oprintf(fp, "\n"); } else { - oprintf(fp, " Supported Voltages: %.1fV\n", + oprintf(fp, " Supported Voltages: %.1f V\n", (float)SMB_PRV_VOLTAGE(p.smbp_voltage) / 10); } if (p.smbp_clkspeed != 0) - oprintf(fp, " External Clock Speed: %uMHz\n", p.smbp_clkspeed); + oprintf(fp, " External Clock Speed: %u MHz\n", p.smbp_clkspeed); else oprintf(fp, " External Clock Speed: Unknown\n"); if (p.smbp_maxspeed != 0) - oprintf(fp, " Maximum Speed: %uMHz\n", p.smbp_maxspeed); + oprintf(fp, " Maximum Socket Speed: %u MHz\n", p.smbp_maxspeed); else - oprintf(fp, " Maximum Speed: Unknown\n"); + oprintf(fp, " Maximum Socket Speed: Unknown\n"); if (p.smbp_curspeed != 0) - oprintf(fp, " Current Speed: %uMHz\n", p.smbp_curspeed); + oprintf(fp, " Current Speed: %u MHz\n", p.smbp_curspeed); else oprintf(fp, " Current Speed: Unknown\n"); @@ -435,7 +446,7 @@ oprintf(fp, " Installed Size: Not Installed\n"); if (c.smba_speed != 0) - oprintf(fp, " Speed: %uns\n", c.smba_speed); + oprintf(fp, " Speed: %u MHz\n", c.smba_speed); else oprintf(fp, " Speed: Unknown\n"); @@ -514,6 +525,11 @@ flag_printf(fp, "Slot Characteristics 2", s.smbl_ch2, sizeof (s.smbl_ch2) * NBBY, smbios_slot_ch2_name, smbios_slot_ch2_desc); + if (s.smbl_group != 0xff) { + oprintf(fp, " Segment Group: %u\n", s.smbl_group); + oprintf(fp, " Bus/Device/Function: %u/%u/%u\n", + s.smbl_bus, s.smbl_device, s.smbl_function); + } } static void @@ -531,6 +547,24 @@ } static void +print_obdevse(smbios_hdl_t *shp, id_t id, FILE *fp) +{ + smbios_obdeve_t o; + (void) smbios_info_obdevse(shp, id, &o); + + oprintf(fp, " Reference Designator: %s\n", o.smbd_name); + oprintf(fp, " Enabled: %c\n", o.smbd_enabled ? 'Y' : 'N'); + oprintf(fp, " Device Type: 0x%x (%s)", + o.smbd_type, smbios_obdev_desc(o.smbd_type)); + oprintf(fp, " Instance: %u\n", o.smbd_instance); + if (o.smbd_group != 0xff) { + oprintf(fp, " Segment Group: %u\n", o.smbd_group); + oprintf(fp, " Bus/Device/Function: %u/%u/%u\n", + o.smbd_bus, o.smbd_device, o.smbd_function); + } +} + +static void print_strtab(smbios_hdl_t *shp, id_t id, FILE *fp) { const char **argv; @@ -689,6 +723,11 @@ else oprintf(fp, " Data Width: Unknown\n"); + if (md.smbmd_rank != 0) { + oprintf(fp, " Rank: %u\n", md.smbmd_rank); + } else { + oprintf(fp, " Rank: Unknown\n"); + } switch (md.smbmd_size) { case -1ull: oprintf(fp, " Size: Unknown\n"); @@ -718,9 +757,13 @@ smbios_memdevice_flag_name, smbios_memdevice_flag_desc); if (md.smbmd_speed != 0) - oprintf(fp, " Speed: %uns\n", md.smbmd_speed); + oprintf(fp, " Speed: %u MHz\n", md.smbmd_speed); else oprintf(fp, " Speed: Unknown\n"); + if (md.smbmd_cfgspeed != 0) + oprintf(fp, " Configured Speed: %u MHz\n", md.smbmd_cfgspeed); + else + oprintf(fp, " Configured Speed: Unknown\n"); oprintf(fp, " Device Locator: %s\n", md.smbmd_dloc); oprintf(fp, " Bank Locator: %s\n", md.smbmd_bloc); @@ -938,10 +981,10 @@ (uint_t)sp->smbstr_id, (ulong_t)sp->smbstr_size); if ((s = smbios_type_name(sp->smbstr_type)) != NULL) - oprintf(fp, " %s", s); + oprintf(fp, " %u %s", sp->smbstr_type, s); else if (sp->smbstr_type > SMB_TYPE_OEM_LO && sp->smbstr_type < SMB_TYPE_OEM_HI) - oprintf(fp, " %s+%u", "SMB_TYPE_OEM_LO", + oprintf(fp, " %u %s+%u",sp->smbstr_type, "SMB_TYPE_OEM_LO", sp->smbstr_type - SMB_TYPE_OEM_LO); else oprintf(fp, " %u", sp->smbstr_type); @@ -996,6 +1039,10 @@ oprintf(fp, "\n"); print_obdevs(shp, sp->smbstr_id, fp); break; + case SMB_TYPE_OBDEVSE: + oprintf(fp, "\n"); + print_obdevse(shp, sp->smbstr_id, fp); + break; case SMB_TYPE_OEMSTR: case SMB_TYPE_SYSCONFSTR: oprintf(fp, "\n");